Digital data is usually stored on a floppy disk, a hard disk or a magnetic tape in different codes or formats. It is well known that a reference clock signal is usually encoded along with the actual data, such as in a floppy disk or a magnetic tape. As a result, a data separator is required to separate the reference clock signal from the actual data and to decode the stored data with the help of the reconstructed reference clock.
Due to the noise and jitters that always accompany the data stream from the disk, and variations in the rotation speed of the disk, the data and the reference clock signals will change from time to time. Consequently, the data separator must be able to accommodate for the changes in the data rate and remain synchronized to the reference clock signal. This task is accomplished in conventional data. separators with a phase-locked loop.
In early days analog phase-locked loops were implemented in data separators, which generally provided acceptable performances. The disadvantages of analog phase-locked loops, however, include high noise level, discrete components that need to be adjusted manually, large circuit size and low reliability. With the advancement of the VLSI technology, therefore, analog phase-locked loops are almost completely replaced by digital phase-locked loops.
A conventional digital phase-locked loop typically employs a high speed counter to generate a clock signal that can be locked to the reference clock signal in the input data stream. The phase of the clock signal can be adjusted to track the variations in time of the reference clock signal. The precision of the reconstructed clock signal is usually determined by the speed of the system clock. The higher the system clock rate, the finer the time steps in variation of the reference clock that the system can resolve. Therefore, it is usually unavoidable to adopt a system clock that is much higher in frequency than the data stream. As a result, cost and power consumption of the system increase significantly.
It is therefore desirable to design a digital phase-locked loop circuit with a system clock frequency about 12 to 16 times that of the data stream, while improving the resolution of the phase of the reconstructed reference clock without further increasing the system clock rate. Zapisek et al. disclosed a data separator in U.S. Pat. No. 4,472,818, issued Sep. 18, 1984, which implemented a digital phase-locked loop that specifically generates a reconstructed reference clock signal having the same phase as the reference clock signal of the input data stream. The main disadvantage with the above invention is its poor precision of the phase of the reconstructed reference clock.
A data separator with a digital phase-locked loop that increases precision and accuracy of the recovered reference clock was disclosed by Nesin et al. in U.S. Pat. No.4,796,280, issued Jan. 3, 1989. The digital phase-locked loop of the above invention uses half period of the system clock to increase the precision of the phase information of the input data stream and exactly simulates the function of an analog phase-locked loop. The circuit also generates a reconstructed reference clock that is synchronized with the input data stream with smallest phase differences possible. The main disadvantage with the above invention is that, by using the half period of the system clock, the precision is increased by only one bit, or equivalent to doubling the frequency of the system clock.
In order to further increase the precision of the digital phase-locked loop without increasing the frequency of the system clock, it is one of the objects of the present invention to provide a circuit that implements a fraction phase predictor to increase the phase information of the input data with a 3-bit fraction phase that can significantly improve the accuracy of the recovered reference clock signal.